1. Field of the Invention
The present invention relates generally to a semiconductor structure and a method for fabricating a semiconductor layout, more particularly, to a semiconductor structure and a method for fabricating a semiconductor layout adopting double patterning technique (DPT).
2. Description of the Prior Art
Integrated circuit (IC) is constructed by devices and interconnections, which are formed by patterned feature indifferent layers. In the fabrication of IC, photolithography has been an essential technique. The photolithography is to form designed patterns such as implantation patterns or layout patterns on at least a photomask, and then to precisely transfer such patterns to a photoresist layer by exposure and development steps. Subsequently, by performing semiconductor processes such as ion implantation, etching process, or deposition, the complicated and sophisticated IC structure is obtained.
Along with miniaturization of semiconductor devices and progress in fabrication of semiconductor device, conventional lithography process meets the bottleneck due to printability and manufacturability. To meet the requirements of device design rules which continue to push the resolution limits of existing processes and tooling, double patterning technique (DPT) is developed and taken as one of the most promising lithography technologies for 32 nanometer (nm) node and 22 nm node patterning since it can increase the half-pitch resolution by up to two times using current infrastructures. Please refer to FIG. 1, which is a schematic drawing illustrating a conventional DPT. As shown in FIG. 1, the DPT decomposes original layout patterns 100 into two masks and applies double exposure patterning to increase the pitch size and thus printability. In detail, one of the masks includes layout patterns 102 and the other includes layout patterns 104, and the layout patterns 102 and the layout patterns 104 compose the original layout patterns 100. When an intact configuration among the original layout patterns 100 has to be split to form the layout pattern 102 and the layout pattern 104 in consideration of the minimum space, which is emphasized by circle A in FIG. 1, such original layout pattern is taken as a to-be-split pattern.
Please refer to FIG. 2, which is a semiconductor structure formed by the conventional DPT. Since the DPT undergoes multiple exposures, overlay control and alignment are always the major concern of the DPT. It is found that overlay control and accurate alignment are more important to the to-be-split pattern. When overlay error or inaccurate alignment occurs, two split patterns obtained by splitting the to-be-split pattern, which should be connected after the DPT, may not be connected to each other. Furthermore, line-end shortening, which is often found in photolithography process, may cause split pattern break as shown in circle B in FIG. 2. Consequently, serious line broken is resulted. Briefly speaking, the to-be-split pattern increases manufacturing cost and complexity due to the overlay control and the line-end shortening issues.
Accordingly, it is still in need to overcome the abovementioned problems and provide a semiconductor structure and a method for fabricating a semiconductor layout.